/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:55:03 2010

 Licensed to :EVALUATION USER:
*/

module RAM_SRAM ( p_reset , m_clock , AD_i , DB_i , DB_o , CS_i , WEN_i , REN_i );
  input p_reset, m_clock;
  input [1:0] AD_i;
  input [7:0] DB_i;
  output [7:0] DB_o;
  input CS_i;
  input WEN_i;
  input REN_i;
  reg [7:0] mem_array [0:3];
  wire _net_0;
  wire _net_1;

   assign  _net_0 = CS_i&WEN_i;
   assign  _net_1 = CS_i&REN_i;

//synthesis translate_off
always @(posedge m_clock or posedge p_reset)
  begin
if ((~_net_1)&_net_1)
 begin $display("Warning: assign collision(RAM_SRAM:DB_o) at %d",$time);
if (~_net_1) $display("assert (~_net_1) at 32\n");
if (_net_1) $display("assert (_net_1) at 30\n");

  end
  end
//synthesis translate_on
   assign  DB_o =
//synthesis translate_off
((~_net_1)&_net_1)? 8'bx :((~_net_1)|_net_1)?
//synthesis translate_on
((~_net_1)?8'b00000000:8'b0)|
    ((_net_1)?mem_array[AD_i]:8'b0)
//synthesis translate_off
:8'bx
//synthesis translate_on
;
always @(posedge m_clock)
  begin
   if (_net_0 )
     mem_array[AD_i] <= DB_i;
end
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:55:03 2010

 Licensed to
*/