In NSL, neither the clock signal nor the reset signal used
in the sequential circuit is described usually.
And, the clock signal automatically generates an input data terminal named “m_clock”,
and the reset signal does it named “p_reset” respectively in the compilation process.
Using the “interface” syntax makes
it possible to cancel the automatic generation of the input data terminal “m_clock” and “p_reset”.
This function is used when the module described in another language is reused,
and it is wanted to control the clock signal and the reset signal explicitly, and so on.
Note:
Regardless of the presence of “interface”, when the sequential circuit is described in the module,
the reset signal name and the clock signal name in the circuit
to be generated are automatically synthesized using the name given by the processing system.
In addition, as for the reset name and the clock name,
the name can be changed by an option at the compilation side.
It is automatically synthesized by “p_reset” and “m_clock” by default.
The description method of “interface” is as follows.
declare Module_name interface {
// Input/output structure element
}
module Module_name {
// Internal structure element
// Part of operation description
}Let’s see Example 40 as an example of the “interface” syntax.
declare ex40_adder4 interface {
input clkin ; // Clock input
input reset ; // Reset input
input add_a[4] ; // Add value A
input add_b[4] ; // Add value B
output result_q[4] ; // Result value Q
}
// #include "ex40_adder4.def"
declare ex40 {
input sysclk ; // Clock input
input sysrst ; // Reset input
input add_a[4] ; // Add value A
input add_b[4] ; // Add value B
output result_q[4] ; // Result value Q
}
module ex40 {
ex40_adder4 adder4 ;
{
// ******** Input signals ********
adder4.clkin = sysclk ;
adder4.reset = sysrst ;
adder4.add_a = add_a ;
adder4.add_b = add_b ;
// ******** Output signals ********
result_q = adder4.result_q ;
}
}
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#include "ex41_synchronize.nsl"
declare ex41 {
input LowerCLK ;
input Access_REQ ;
output Access_ACK ;
input Access_FIN ;
}
module ex41 {
reg internal_REQ[3] = 0 ;
/* ******** Declare lower module ******** */
EX41_Synchronize sync_func ;
{
internal_REQ := { internal_REQ[1:0], Access_REQ } ; // 3stage shift-register
sync_func.m_clock = LowerCLK ; // Explicit CLOCK define.
// BusREQ_in will be asserted at 3clock delayed from Access_REQ is asserter.
sync_func.BusREQ_in = internal_REQ[2] ;
sync_func.BusACK_in = Access_FIN ;
Access_ACK = sync_func.BusBUSY_out ;
}
}
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