/* ************************************************************ */
declare HiZ_sample_INOUT    {
    inout       HiZIO_pin ;

    output      IN_from_HiZIO ;
    input       OUT_to_HiZIO ;

    func_in     OEN() ;     //  0 : BIDIR.out = HiZ, BIDIR pin value -> IN pin.
                            //  1 : OUT pin value -> BIDIR pin,
}
/* ************************************************************ */

module  HiZ_sample_INOUT    {

/* ************************************************************ */
/*
// Equation sample #1
    {
        if ( OEN )  HiZIO_pin = OUT_to_HiZIO ;  // Data output at OEN is 'H'
        IN_from_HiZIO = HiZIO_pin ;             // Always reflect.
    }
*/
/* ************************************************************ */
/*
// Equation sample #2
    any {
        OEN     : HiZIO_pin = OUT_to_HiZIO ;
                // Output internal signal to PIN at an 'OEN' is 'H'
        else    : IN_from_HiZIO = HiZIO_pin ;
                // PIN value is reflected to IN_from_HiZIO pin.
                //  - But, a pin of declared as output, right side value is
                //    reflected to left side even if 'else' situaion.
    }
*/
/* ************************************************************ */

// Equation sample #3
    {
        IN_from_HiZIO = HiZIO_pin ;     // Always reflect.
    }

    function    OEN {
        HiZIO_pin = OUT_to_HiZIO ;
                    // Output internal signal to PIN at an 'OEN' is 'H'
    }

}