NSL Core on command line can use options as follows

• -O,-O1 : Optimize level 1 (Automatic setting options as follows)
  • -opt_sel
  • -opt_reg
• -O2 : Optimize level 2 (Automatic setting options as follows)
  • -gray
  • -scond
  • -opt_sel
  • -opt_reg
  • -opt_vhdl
• -sim : Simuration mode (Output Undriven signal when conflict inputs)
• -sync_res : Generate synchronous reset signal
• -neg_res : Use negative reset
• -neg_clk : Use negative(falling) edge trigger
• -und 0 : Not driving signal force set 0 or 1,u,x,z
• -psddly : Verilog HDL assign insert pseudo delay
• -vasy : Generate Alliance compatible VHDL file
• -split : Output files for each modules
• -p : Add prefix signal names
• -clock_name name : Change clock signal name ‘clkname’
• -reset_name name : Change reset signal name ‘rstname’
• -gray : Use gray code counter in state machines
• -scond : Generate single net of substitution conditions
• -opt_sel : Substitution of selector is changed to AND/OR
• -opt_reg : Substitution of register is changed to AND/OR
• -target target_module_name : Module name given to the simulation main routine is designated ‘target_module_name’
• -verisim : Genarate simulation main routine
• -verisim2 : Genarate Verilog HDL source and simulation main routine
• -test_bench module_name : Designate module name ‘module_name’ in the simulation main routine
• -default_nettype type_name : Type name given to ‘`default_nettype’ directive in Verilog HDL is designated ‘type_name’