/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 18:15:18 2010

 Licensed to :EVALUATION USER:
*/

module VAR_IF ( p_reset , m_clock , A_i , B_i , Enb_i , Check_i , Q_AND , Q_OR , Q_ExOR , Q_AisH , Q_BisL );
  input p_reset, m_clock;
  input A_i;
  input B_i;
  input Enb_i;
  input Check_i;
  output Q_AND;
  output Q_OR;
  output Q_ExOR;
  output Q_AisH;
  output Q_BisL;
  wire if_statement_check;
  wire _net_0;
  wire _net_1;
  wire _net_2;
  wire _net_3;

   assign  if_statement_check = Check_i&Enb_i;
   assign  _net_0 = A_i&B_i;
   assign  _net_1 = A_i|B_i;
   assign  _net_2 = A_i^B_i;
   assign  _net_3 = ~B_i;
   assign  Q_AND = if_statement_check&_net_0;
   assign  Q_OR = if_statement_check&_net_1;
   assign  Q_ExOR = if_statement_check&_net_2;
   assign  Q_AisH = if_statement_check&A_i;
   assign  Q_BisL = if_statement_check&_net_3;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 18:15:18 2010

 Licensed to
*/