/* ************************************************************ */
declare func_seq_test {
    input       Ain[4] ;
    input       Bin[4] ;
    output      Qout[8] ;

    func_in Mult( Ain, Bin ) ;
        // Mult:Control input signal. Request for execute a multiply operation.
    func_out    Comp( Qout ) ;
        // Comp:Control output signal. Indicates multiply operation is finished.
}

/* ************************************************************ */
/* ************************************************************ */

module  func_seq_test {

    reg         temp_result[8] = 8'h00 ;    // Define registerd signal
                        //      A registerd signal can assing initial value.
//  wire        temp_result[8] ;            // Define wired signal
                        //      A wired signal does not need initial value.

// Declare internal control function for multiply operation
    func_self   exec_mult() ;   // func_self [Name of internal control func]

// Equation of sequential operation machine
    function    Mult    seq {
    // 0 clock
        exec_mult() ;                       // Launch internal control function
    // 1 clock
        {
            Qout = temp_result[7:0] ;       // Data out via output pin
            Comp() ;        // Drive a control output signal of 'Comp()' pin.
        }
    }

// Equation of multiply function
    function    exec_mult {
        temp_result := Ain[3:0] * Bin[3:0] ;    // Operation : register mode.
//      temp_result = Ain[3:0] * Bin[3:0] ;     // Operation : wire mode.
    }

}       // End of module

/*
    Upper module : Instanciate 'func_seq_test'
*/
/* ************************************************************ */
/* ************************************************************ */
/* ************************************************************ */
declare     top {
    input       a[4] ;          // Data-bus a[3:0]
    input       b[4] ;          // Data-bus b[3:0]

    output      q[8] ;

    func_in go ;            // Control input signal.
}

module  top {
    func_seq_test   DUT ;
                    // Instanciate a 'func_seq' module as name of 'DUT'.

// Define two-parameter for multiply module
    function    go  {
        DUT.Mult( Ain = a, Bin = b ) ;
    }

// Data out at control output signal of 'DUT.comp' will be asserted.
    function    DUT.Comp    {
        q = DUT.Qout ;
    }

}