/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:01 2010

 Licensed to :EVALUATION USER:
*/

module ADDER4_async ( p_reset , m_clock , A_in , B_in , Q_out , exec , done );
  input p_reset, m_clock;
  input [3:0] A_in;
  input [3:0] B_in;
  output [3:0] Q_out;
  input exec;
  output done;

   assign  Q_out =
//synthesis translate_off
(exec)?
//synthesis translate_on
((exec)?(A_in)+(B_in):4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  done = exec;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:01 2010

 Licensed to
*/