/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:17 2010

 Licensed to :EVALUATION USER:
*/

module ADDER4_sync ( p_reset , m_clock , A_in , B_in , Q_out , exec , done );
  input p_reset, m_clock;
  input [3:0] A_in;
  input [3:0] B_in;
  output [3:0] Q_out;
  input exec;
  output done;
  reg [3:0] reg_Q;
  reg adder_finish;
  wire _proc_adder_finish_set;
  wire _proc_adder_finish_reset;

   assign  _proc_adder_finish_set = exec;
   assign  _proc_adder_finish_reset = adder_finish;
   assign  Q_out =
//synthesis translate_off
(adder_finish)?
//synthesis translate_on
((adder_finish)?reg_Q:4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  done = adder_finish;
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     reg_Q <= 4'b0000;
else if (exec)
      reg_Q <= (A_in)+(B_in);
end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     adder_finish <= 1'b0;
else if (_proc_adder_finish_set|_proc_adder_finish_reset)
      adder_finish <= _proc_adder_finish_set;
end
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:17 2010

 Licensed to
*/