/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:54:09 2010

 Licensed to :EVALUATION USER:
*/

module FF_4bit_ar ( p_reset , m_clock , D_in , ENB_in , Q_out );
  input p_reset, m_clock;
  input [3:0] D_in;
  input ENB_in;
  output [3:0] Q_out;
  reg [3:0] Dtype_FF;

   assign  Q_out = Dtype_FF;
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     Dtype_FF <= 4'b1010;
else if (ENB_in)
      Dtype_FF <= D_in;
end
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:54:10 2010

 Licensed to
*/