/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:54:04 2010

 Licensed to :EVALUATION USER:
*/

module FF_1bit_sr ( p_reset , m_clock , D_in , SR_in , ENB_in , Q_out );
  input p_reset, m_clock;
  input D_in;
  input SR_in;
  input ENB_in;
  output Q_out;
  reg Dtype_FF;

   assign  Q_out = Dtype_FF;
always @(posedge m_clock)
  begin

//synthesis translate_off
if (((~SR_in)&ENB_in)&SR_in)   Dtype_FF <= 1'bx;
  else
//synthesis translate_on
if ((~SR_in)&ENB_in)
      Dtype_FF <= D_in;
else if (SR_in)
      Dtype_FF <= 1'b0;
end

//synthesis translate_off
always @(posedge m_clock)
  begin
if ((((~SR_in)&ENB_in)|SR_in=='b1) ||
 (((~SR_in)&ENB_in)|SR_in=='b0) ) begin
 if (((~SR_in)&ENB_in)&SR_in)
 begin $display("Warning: assign collision(FF_1bit_sr:Dtype_FF) at %d",$time);

  end
 end
 else
 $display("Warning: register set hazard(FF_1bit_sr:Dtype_FF) at %d",$time);
  end
//synthesis translate_on
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:54:04 2010

 Licensed to
*/