/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:56 2010

 Licensed to :EVALUATION USER:
*/

module FF_1bit_ar ( p_reset , m_clock , D_in , ENB_in , Q_out );
  input p_reset, m_clock;
  input D_in;
  input ENB_in;
  output Q_out;
  reg Dtype_FF;

   assign  Q_out = Dtype_FF;
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     Dtype_FF <= 1'b0;
else
//synthesis translate_off
if ((~ENB_in)&ENB_in)   Dtype_FF <= 1'bx;
  else
//synthesis translate_on
if (~ENB_in)
      Dtype_FF <= Dtype_FF;
else if (ENB_in)
      Dtype_FF <= D_in;
end

//synthesis translate_off
always @(posedge m_clock)
  begin
if (((~ENB_in)|ENB_in=='b1) ||
 ((~ENB_in)|ENB_in=='b0) ) begin
 if ((~ENB_in)&ENB_in)
 begin $display("Warning: assign collision(FF_1bit_ar:Dtype_FF) at %d",$time);

  end
 end
 else
 $display("Warning: register set hazard(FF_1bit_ar:Dtype_FF) at %d",$time);
  end
//synthesis translate_on
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:56 2010

 Licensed to
*/