/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:54:23 2010

 Licensed to :EVALUATION USER:
*/

module bidirect_1bit ( p_reset , m_clock , PortA , PortB , DIR , OEN );
  input p_reset, m_clock;
inout PortA;
inout PortB;
  input DIR;
  input OEN;
  wire _net_0;

   assign  _net_0 = ~DIR;
   assign  PortA = (OEN&_net_0)? ((OEN&_net_0)?PortB:1'bZ):1'bz;
   assign  PortB = (OEN&(~_net_0))? ((OEN&(~_net_0))?PortA:1'bZ):1'bz;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:54:23 2010

 Licensed to
*/