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About NSL
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NSL Core Command line options
NSL Sample
Beginners
3 input AND – OR gate
AOI.nsl
AOI.v
4bit binary counter
CNT4.nsl
CNT4.v
4bit F/F sample with SR ( Databus sample )
FF_4bit_SR.nsl
FF_4bit_SR.v
8word x 8bit width PROM sample
RAM_PROM.nsl
RAM_PROM.v
NSL code to Verilog code parameter passing
Middle
Function
Tutorial
00. NSL outline
01. I/O structure element
02. Internal terminal and register
03. Action description
04. Control terminal
05. Submodule
06. Procedure
07. State variable
08. Memory
09. Interface
10. System task
11. Directive
12.Structure
About us
Company Profile
Directors
Message from Chairman
About NSL
Support
NSL Core Command line options
NSL Sample
Beginners
3 input AND – OR gate
AOI.nsl
AOI.v
4bit binary counter
CNT4.nsl
CNT4.v
4bit F/F sample with SR ( Databus sample )
FF_4bit_SR.nsl
FF_4bit_SR.v
8word x 8bit width PROM sample
RAM_PROM.nsl
RAM_PROM.v
NSL code to Verilog code parameter passing
Middle
Function
Tutorial
00. NSL outline
01. I/O structure element
02. Internal terminal and register
03. Action description
04. Control terminal
05. Submodule
06. Procedure
07. State variable
08. Memory
09. Interface
10. System task
11. Directive
12.Structure
contact
2 input Exclusive OR gate
File name
ExOR2.nsl
Function
2input exclusive OR gate
Signal description
A_i = Input A
B_i = Input B
Q_o = Output
NSL
Verilog
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