/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 19:50:36 2010
 Licensed to :NON PROFIT USER:
*/

module AND2 ( p_reset , m_clock , A_i , B_i , Q_o );
  input p_reset, m_clock;
  input A_i;
  input B_i;
  output Q_o;

   assign  Q_o = A_i&B_i;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 19:50:36 2010
 Licensed to
*/