/*
 Produced by NSL Core(version=20110725), IP ARCH, Inc. Wed Sep 07 17:01:09 2011
 Licensed to :LIMITED EVALUATION USER:
*/
/*
 EVALUATION COPY!   DO NOT USE ANY PART OF THIS FILE FOR COMMERCIAL PRODUCTS.
*/

module MAJORITY3 ( p_reset , m_clock , A_i , B_i , C_i , Q_o );
  input p_reset, m_clock;
  wire p_reset, m_clock;
  input A_i;
  wire A_i;
  input B_i;
  wire B_i;
  input C_i;
  wire C_i;
  output Q_o;
  wire Q_o;
  wire [2:0] in_value;
  wire _net_0;
  wire _net_1;
  wire _net_2;
  wire _net_3;

   assign  in_value = {A_i,B_i,C_i};
   assign  _net_0 = (in_value)==(3'b111);
   assign  _net_1 = (in_value)==(3'b110);
   assign  _net_2 = (in_value)==(3'b101);
   assign  _net_3 = (in_value)==(3'b011);

// synthesis translate_off

// synopsys translate_off
always @(posedge m_clock or posedge p_reset)
  begin
if ((((((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3))&_net_3)|((((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3))|_net_3)&_net_2))|(((((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3))|_net_3)|_net_2)&_net_1))|((((((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3))|_net_3)|_net_2)|_net_1)&_net_0))
 begin $display("Warning: assign collision(MAJORITY3:Q_o) at %d",$time);
if ((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3)) $display("assert ((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3)) line 33 at %d\n",$time);
if (_net_3) $display("assert (_net_3) line 29 at %d\n",$time);
if (_net_2) $display("assert (_net_2) line 30 at %d\n",$time);
if (_net_1) $display("assert (_net_1) line 31 at %d\n",$time);
if (_net_0) $display("assert (_net_0) line 32 at %d\n",$time);
 end
 end

// synthesis translate_on

// synopsys translate_on
   assign  Q_o =
// synthesis translate_off

// synopsys translate_off
((((((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3))&_net_3)|((((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3))|_net_3)&_net_2))|(((((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3))|_net_3)|_net_2)&_net_1))|((((((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3))|_net_3)|_net_2)|_net_1)&_net_0))? 1'bx :((((((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3))|_net_3)|_net_2)|_net_1)|_net_0)?
// synthesis translate_on

// synopsys translate_on
(((((~_net_0)&(~_net_1))&(~_net_2))&(~_net_3))?1'b0:1'b0)|
    ((_net_3)?1'b1:1'b0)|
    ((_net_2)?1'b1:1'b0)|
    ((_net_1)?1'b1:1'b0)|
    ((_net_0)?1'b1:1'b0)
// synthesis translate_off

// synopsys translate_off
:1'bx
// synthesis translate_on

// synopsys translate_on
;
endmodule
/*
 Produced by NSL Core(version=20110725), IP ARCH, Inc. Wed Sep 07 17:01:09 2011
 Licensed to :LIMITED EVALUATION USER:
*/