/* ************************************************************ */
declare RAM_FIFO {
input DB_i[8] ; // Write Data (in)
output DB_o[8] ; // Read Data (out)
input WEN_i ; // Write enable (in)
input REN_i ; // Read enable (in)
output FULL ; // FIFO full flag.
output EMPTY ; // FIFO empty flag.
}
/* ************************************************************ */
// Declare module
module RAM_FIFO {
/* ************************************************************ */
// Internal operation signals
mem mem_array [16][8] = { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 } ;
// Declare memory array with INIT.
reg reg_DB_o[8] ;
reg wr_ptr[4] = 0 ; // Write pointer ( current )
reg rd_ptr[4] = 0 ; // Read pointer ( current )
wire next_wr_ptr[4] ;
wire next_rd_ptr[4] ;
wire internal_FULL ;
wire internal_EMPTY ;
func_self Check_FULL_flag() ;
func_self Check_EMPTY_flag() ;
/* ************************************************************ */
// Equation
{
// ************************ //
// FIFO write side.
if ( WEN_i & ~internal_FULL ) {
mem_array[wr_ptr] := DB_i ; // Store a current write data to memory array.
wr_ptr := next_wr_ptr ; // Update NEW write pointer
}
next_wr_ptr = wr_ptr + 4'b1 ;
Check_FULL_flag() ;
// ************************ //
// FIFO read side.
if ( REN_i & ~internal_EMPTY ) {
reg_DB_o := mem_array[rd_ptr] ;
// Read-out memory array to internal output regs.
rd_ptr := next_rd_ptr ; // Update NEW write pointer
}
DB_o = reg_DB_o ;
next_rd_ptr = rd_ptr + 4'b1 ;
Check_EMPTY_flag() ;
FULL = internal_FULL ;
EMPTY = internal_EMPTY ;
}
func Check_FULL_flag {
any {
next_wr_ptr == rd_ptr : internal_FULL = 1'b1 ; // Set FULL flag.
else : internal_FULL = 1'b0 ;
}
}
func Check_EMPTY_flag {
any {
rd_ptr == wr_ptr : internal_EMPTY = 1'b1 ; // Set FULL flag.
else : internal_EMPTY = 1'b0 ;
}
}
/* ************************************************************ */
}