/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:54:57 2010

 Licensed to :EVALUATION USER:
*/

module RAM_PROM ( p_reset , m_clock , AD_i , DB_o1 , DB_o2 , CS_i , REN_i );
  input p_reset, m_clock;
  input [2:0] AD_i;
  output [7:0] DB_o1;
  output [7:0] DB_o2;
  input CS_i;
  input REN_i;
  reg [7:0] mem_array [0:7];
  reg [7:0] clocked_rdout;
  wire _net_0;
  wire _net_1;

   assign  _net_0 = CS_i&REN_i;
   assign  _net_1 = CS_i&REN_i;

//synthesis translate_off
always @(posedge m_clock or posedge p_reset)
  begin
if ((~_net_0)&_net_0)
 begin $display("Warning: assign collision(RAM_PROM:DB_o1) at %d",$time);
if (~_net_0) $display("assert (~_net_0) at 44\n");
if (_net_0) $display("assert (_net_0) at 42\n");

  end
  end
//synthesis translate_on
   assign  DB_o1 =
//synthesis translate_off
((~_net_0)&_net_0)? 8'bx :((~_net_0)|_net_0)?
//synthesis translate_on
((~_net_0)?8'b00000000:8'b0)|
    ((_net_0)?mem_array[AD_i]:8'b0)
//synthesis translate_off
:8'bx
//synthesis translate_on
;
   assign  DB_o2 = clocked_rdout;
initial begin
    mem_array[0] <= 8'b00000001;
    mem_array[1] <= 8'b00000010;
    mem_array[2] <= 8'b00000011;
    mem_array[3] <= 8'b00000100;
    mem_array[4] <= 8'b10010110;
    mem_array[5] <= 8'b00111000;
    mem_array[6] <= 8'b11111110;
    mem_array[7] <= 8'b10101100;
end
always @(posedge m_clock)
  begin

//synthesis translate_off
if ((~_net_1)&_net_1)   clocked_rdout <= 8'bx;
  else
//synthesis translate_on
if (~_net_1)
      clocked_rdout <= 8'b00000000;
else if (_net_1)
      clocked_rdout <= mem_array[AD_i];
end

//synthesis translate_off
always @(posedge m_clock)
  begin
if (((~_net_1)|_net_1=='b1) ||
 ((~_net_1)|_net_1=='b0) ) begin
 if ((~_net_1)&_net_1)
 begin $display("Warning: assign collision(RAM_PROM:clocked_rdout) at %d",$time);

  end
 end
 else
 $display("Warning: register set hazard(RAM_PROM:clocked_rdout) at %d",$time);
  end
//synthesis translate_on
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:54:57 2010

 Licensed to
*/