/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:12 2010

 Licensed to :EVALUATION USER:
*/

module adder4 ( p_reset , m_clock , A_in , B_in , Q_out , exec , done );
  input p_reset, m_clock;
  input [3:0] A_in;
  input [3:0] B_in;
  output [3:0] Q_out;
  input exec;
  output done;

   assign  Q_out =
//synthesis translate_off
(exec)?
//synthesis translate_on
((exec)?(A_in)+(B_in):4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  done = exec;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:12 2010

 Licensed to
*/

module ADDER4_func_call ( p_reset , m_clock , Add_A_in , Add_B_in , Add_result , Add_exec , Add_done );
  input p_reset, m_clock;
  input [3:0] Add_A_in;
  input [3:0] Add_B_in;
  output [3:0] Add_result;
  input Add_exec;
  output Add_done;
  wire _u_adder4_done;
  wire _u_adder4_exec;
  wire [3:0] _u_adder4_Q_out;
  wire [3:0] _u_adder4_B_in;
  wire [3:0] _u_adder4_A_in;
adder4 u_adder4 (.p_reset(p_reset), .m_clock(m_clock), .done(_u_adder4_done), .exec(_u_adder4_exec), .Q_out(_u_adder4_Q_out), .B_in(_u_adder4_B_in), .A_in(_u_adder4_A_in));

   assign  _u_adder4_exec = Add_exec;
   assign  _u_adder4_B_in =
//synthesis translate_off
(Add_exec)?
//synthesis translate_on
((Add_exec)?Add_B_in:4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  _u_adder4_A_in =
//synthesis translate_off
(Add_exec)?
//synthesis translate_on
((Add_exec)?Add_A_in:4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  Add_result =
//synthesis translate_off
(Add_exec)?
//synthesis translate_on
((Add_exec)?_u_adder4_Q_out:4'b0)
//synthesis translate_off
:4'bx
//synthesis translate_on
;
   assign  Add_done = Add_exec;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:12 2010

 Licensed to
*/