/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:55:32 2010

 Licensed to :EVALUATION USER:
*/

module PAR32 ( p_reset , m_clock , Data_i , Parity_o1 , Parity_o2 );
  input p_reset, m_clock;
  input [31:0] Data_i;
  output Parity_o1;
  output Parity_o2;
  wire tmp_Parity_o1;
  wire tmp_Parity_o2;
  wire tmp_Parity_o3;
  wire tmp_Parity_o4;

   assign  tmp_Parity_o1 = {(((((((Data_i[7])^(Data_i[6]))^(Data_i[5]))^(Data_i[4]))^(Data_i[3]))^(Data_i[2]))^(Data_i[1]))^(Data_i[0])};
   assign  tmp_Parity_o2 = {(((((((Data_i[15])^(Data_i[14]))^(Data_i[13]))^(Data_i[12]))^(Data_i[11]))^(Data_i[10]))^(Data_i[9]))^(Data_i[8])};
   assign  tmp_Parity_o3 = {(((((((Data_i[23])^(Data_i[22]))^(Data_i[21]))^(Data_i[20]))^(Data_i[19]))^(Data_i[18]))^(Data_i[17]))^(Data_i[16])};
   assign  tmp_Parity_o4 = {(((((((Data_i[31])^(Data_i[30]))^(Data_i[29]))^(Data_i[28]))^(Data_i[27]))^(Data_i[26]))^(Data_i[25]))^(Data_i[24])};
   assign  Parity_o1 = ((tmp_Parity_o1^tmp_Parity_o2)^tmp_Parity_o3)^tmp_Parity_o4;
   assign  Parity_o2 = ^(Data_i[31:0]);
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:55:32 2010

 Licensed to
*/