/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:36 2010

 Licensed to :EVALUATION USER:
*/

module CNT4 ( p_reset , m_clock , PARAM_in , LOAD_in , ENB_in , CARRY_in , Q_out , CARRY_out );
  input p_reset, m_clock;
  input [3:0] PARAM_in;
  input LOAD_in;
  input ENB_in;
  input CARRY_in;
  output [3:0] Q_out;
  output CARRY_out;
  reg [3:0] Counter_4bit;
  wire _net_0;

   assign  _net_0 = (Counter_4bit)==(4'b1111);
   assign  Q_out = Counter_4bit;
   assign  CARRY_out = _net_0;
always @(posedge m_clock)
  begin

//synthesis translate_off
if ((CARRY_in&ENB_in)&LOAD_in)   Counter_4bit <= 4'bx;
  else
//synthesis translate_on
if (CARRY_in&ENB_in)
      Counter_4bit <= (Counter_4bit)+(4'b0001);
else if (LOAD_in)
      Counter_4bit <= PARAM_in;
end

//synthesis translate_off
always @(posedge m_clock)
  begin
if (((CARRY_in&ENB_in)|LOAD_in=='b1) ||
 ((CARRY_in&ENB_in)|LOAD_in=='b0) ) begin
 if ((CARRY_in&ENB_in)&LOAD_in)
 begin $display("Warning: assign collision(CNT4:Counter_4bit) at %d",$time);

  end
 end
 else
 $display("Warning: register set hazard(CNT4:Counter_4bit) at %d",$time);
  end
//synthesis translate_on
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:53:36 2010

 Licensed to
*/