/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:56:07 2010

 Licensed to :EVALUATION USER:
*/

module TTL_74245_TypeA ( p_reset , m_clock , Port_A , Port_B , DIR , nOE );
  input p_reset, m_clock;
inout [7:0] Port_A;
inout [7:0] Port_B;
  input DIR;
  input nOE;
  wire output_enable;
  wire _net_0;
  wire _net_1;

   assign  output_enable = _net_0;
   assign  _net_0 = ~nOE;
   assign  _net_1 = ~DIR;
   assign  Port_A = (output_enable&(~_net_1))? ((output_enable&(~_net_1))?Port_B:8'bZ):8'bz;
   assign  Port_B = (output_enable&_net_1)? ((output_enable&_net_1)?Port_A:8'bZ):8'bz;
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:56:07 2010

 Licensed to
*/