/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:54:48 2010

 Licensed to :EVALUATION USER:
*/

module RAM_FIFO ( p_reset , m_clock , DB_i , DB_o , WEN_i , REN_i , FULL , EMPTY );
  input p_reset, m_clock;
  input [7:0] DB_i;
  output [7:0] DB_o;
  input WEN_i;
  input REN_i;
  output FULL;
  output EMPTY;
  reg [7:0] mem_array [0:15];
  reg [7:0] reg_DB_o;
  reg [3:0] wr_ptr;
  reg [3:0] rd_ptr;
  wire [3:0] next_wr_ptr;
  wire [3:0] next_rd_ptr;
  wire internal_FULL;
  wire internal_EMPTY;
  wire Check_FULL_flag;
  wire Check_EMPTY_flag;
  wire _net_0;
  wire _net_1;
  wire _net_2;
  wire _net_3;

   assign  next_wr_ptr = (wr_ptr)+(4'b0001);
   assign  next_rd_ptr = (rd_ptr)+(4'b0001);

//synthesis translate_off
always @(posedge m_clock or posedge p_reset)
  begin
if ((Check_FULL_flag&(~_net_2))&Check_FULL_flag&_net_2)
 begin $display("Warning: assign collision(RAM_FIFO:internal_FULL) at %d",$time);
if (Check_FULL_flag&(~_net_2)) $display("assert (Check_FULL_flag&(~_net_2)) at 71\n");
if (Check_FULL_flag&_net_2) $display("assert (Check_FULL_flag&_net_2) at 70\n");

  end
  end
//synthesis translate_on
   assign  internal_FULL =
//synthesis translate_off
((Check_FULL_flag&(~_net_2))&Check_FULL_flag&_net_2)? 1'bx :((Check_FULL_flag&(~_net_2))|(Check_FULL_flag&_net_2))?
//synthesis translate_on
((Check_FULL_flag&(~_net_2))?1'b0:1'b0)|
    ((Check_FULL_flag&_net_2)?1'b1:1'b0)
//synthesis translate_off
:1'bx
//synthesis translate_on
;

//synthesis translate_off
always @(posedge m_clock or posedge p_reset)
  begin
if ((Check_EMPTY_flag&(~_net_3))&Check_EMPTY_flag&_net_3)
 begin $display("Warning: assign collision(RAM_FIFO:internal_EMPTY) at %d",$time);
if (Check_EMPTY_flag&(~_net_3)) $display("assert (Check_EMPTY_flag&(~_net_3)) at 78\n");
if (Check_EMPTY_flag&_net_3) $display("assert (Check_EMPTY_flag&_net_3) at 77\n");

  end
  end
//synthesis translate_on
   assign  internal_EMPTY =
//synthesis translate_off
((Check_EMPTY_flag&(~_net_3))&Check_EMPTY_flag&_net_3)? 1'bx :((Check_EMPTY_flag&(~_net_3))|(Check_EMPTY_flag&_net_3))?
//synthesis translate_on
((Check_EMPTY_flag&(~_net_3))?1'b0:1'b0)|
    ((Check_EMPTY_flag&_net_3)?1'b1:1'b0)
//synthesis translate_off
:1'bx
//synthesis translate_on
;
   assign  Check_FULL_flag = 1'b1;
   assign  Check_EMPTY_flag = 1'b1;
   assign  _net_0 = WEN_i&(~internal_FULL);
   assign  _net_1 = REN_i&(~internal_EMPTY);
   assign  _net_2 = (next_wr_ptr)==(rd_ptr);
   assign  _net_3 = (rd_ptr)==(wr_ptr);
   assign  DB_o = reg_DB_o;
   assign  FULL = internal_FULL;
   assign  EMPTY = internal_EMPTY;
initial begin
    mem_array[0] <= 8'b00000000;
    mem_array[1] <= 8'b00000000;
    mem_array[2] <= 8'b00000000;
    mem_array[3] <= 8'b00000000;
    mem_array[4] <= 8'b00000000;
    mem_array[5] <= 8'b00000000;
    mem_array[6] <= 8'b00000000;
    mem_array[7] <= 8'b00000000;
    mem_array[8] <= 8'b00000000;
    mem_array[9] <= 8'b00000000;
    mem_array[10] <= 8'b00000000;
    mem_array[11] <= 8'b00000000;
    mem_array[12] <= 8'b00000000;
    mem_array[13] <= 8'b00000000;
    mem_array[14] <= 8'b00000000;
    mem_array[15] <= 8'b00000000;
end
always @(posedge m_clock)
  begin
   if (_net_0 )
     mem_array[wr_ptr] <= DB_i;
end
always @(posedge m_clock)
  begin
if (_net_1)
      reg_DB_o <= mem_array[rd_ptr];
end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     wr_ptr <= 4'b0000;
else if (_net_0)
      wr_ptr <= next_wr_ptr;
end
always @(posedge m_clock or posedge p_reset)
  begin
if (p_reset)
     rd_ptr <= 4'b0000;
else if (_net_1)
      rd_ptr <= next_rd_ptr;
end
endmodule
/*
 Produced by NSL Core, IP ARCH, Inc. Fri Jun 04 17:54:49 2010

 Licensed to
*/