1) Design Flow by using NSL Core+
This is a guide about Design Flow (Synthesis and Simulation) by using NSL Core+.(5 minutes)
- Sample model
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nsl_tutorial_01_crc.zip（2.5KB）
NSL/
・crc32_nsl.nsh: Declaration of modules
・crc32_nsl.nsl : Definition of modules
・toplevel.nslsimulation/
・ tb.v : Testbench which generates the clock and the reset by verilog description
