10. System task

NSL can use the Verilog-HDL/SystemC compatible system task only for the synthesis into
Verilog-HDL and SystemC.

The system task is a syntax to mainly assist debugging, and it is used for the simulation.
The following Table ? shows the system tasks that can be used by NSL.
In case of NSL, the underscore “_” is applied instead of “$” due to the synthesis.

<<Table 10.Corresponding table by language of system task>>
System task
command
Corresponding
system task of Verilog-HDL
Corresponding
function of SystemC
Meaning
_display
_monitor
_finish
_readmemb
_readmemh
$display
$monitor
$finish
$readmemb
$readmemh
printf()
printf()
sc_stop()
-
-
Message and value are indicated on
the command line.
Message and value are indicated on
the command line only when value of
the specified signal changed.
End of simulation
Readout of memory file(in binary)
Readout of memory file(in hexadecimal)

Usage of the system task is the same as Verilog-HDL. The system task can be used just
like Verilog-HDL now by applying the underscore “_” instead of “$”.
In addition, since this syntax is provided for the simulation purpose, the system task part
is not reflected in the real circuit when a module that includes a system task was logically
synthesized.

<<Example 43.monitor & display>>
declare ex43 {
    input a[4], b[4] ;
    output f[4] ;
}
module ex43 {
    reg trigger[4] = 0 ;
    reg r1[4] = 0 ;
    proc_name proc1, proc2 ;

    trigger := { trigger[3:1], 0b1 } ;
    if(trigger == 0b0111) proc1() ;

    proc proc1 {
        r1 := r1 + 0x1;

        if(r1 > 10) proc2() ;

        _display("a = %d, b = %d", a, b) ;
        _monitor("r1 = %d", r1) ;
    }
    proc proc2 {
        f = r1 ;
        finish() ;
    }
}

The system task “finish” is a command that ends a simulation.
A example of the system task “finish” is presented as follows.

<<example. 44 finish>>
declare ex44 {
    func_in exec_add ;
}
module ex44 {
    reg sum[8] = 0 ;
    reg cnt[4] = 0 ;

    function exec_add seq {
        for(cnt:=0; cnt<10; cnt++) {
            sum := sum + 0x01 ;
            if(cnt==0b0110) _finish() ;
        }
    }
}

“readmemb” and “readmemh” are the system task that loads an external file as the initial
value of the memory.
Representing a sequence in the external file, it can be used by relating the file to it with this
system task.
The external file writes in the sequence in ASCII file text.
It reads in with “readmemb” when the sequence is a binary number, and it reads in with
“readmemh” for a hexadecimal number.

Next, a example of the system task “readmemh” is presented.

<<example.45 readmemh>>
declare ex45 {
    input in_adr[8], in_data[8] ;
    output outdata[8] ;
    func_in write(in_adr, in_data) ;
    func_in read(in_adr) ;
}
module ex45 {
    mem memory[256][8] ;

    alt {
        write : memory[in_adr] := in_data ;
        read  : outdata = memory[in_adr] ;
    }

    _readmemh("neko.txt", memory);
}