2. Internal terminal and register

In Chapter 2, the internal terminal and the register are explained.
The internal terminal and the register use the declaration command listed in Table 8.

<<Table 2-1.Internal terminal and register>>
Declaration command Meaning
wire
reg
Internal terminal
Register

2-1. Explanation of internal terminal

The internal terminal is a syntax that performs the role of “wiring”.
It is used for the purpose to increase a signal to multiple ones, and to subserve the operation.

The value transferred to an internal terminal can be used at the same clock as when it was transferred.
And, it becomes a state in which the value is indefinite (indeterminate) during the time
when no value is transferred to the internal terminal.

Declaration method of the internal terminal is as follows.

wire Internal_terminal_name [bit_width]

The bit width can be omitted, and it is decided to one bit when omitted.
In addition, it describes as follows using “=” when a value and a data are assigned to “wire”.

Internal_terminal_name = Value

Let’s see Example 3 as a usage example of the internal terminal.

<<Example 3. Usage example of internal terminal>>
declare ex03 {
   input a, b ;
   output f ;
}
module ex03 {
   wire c, d ; //Declaration of wire c,d

   c =  a & ~b ; //Expression 1
   d = ~a & b ;  //Expression 2
   f =  c | d ;  //Expression 3
}

The Example 3 indicates a module that has “declaration of data terminal”,
“declaration of internal terminal”, and “common action description”.

Since the hardware description language operates in parallel,
the multiple operations that were described to a common action description are executed at the same time.

Expression 1 of Example 3 indicates an operation that
“logical AND of “a” and “false b” is assigned to the internal terminal c”.
Next, Expression 2 indicates an operation that
“logical AND of “false a” and “b” is assigned to the internal terminal d”.
And, Expression 3 indicates an operation that
“logical OR of “c” and “d” is assigned to the data output terminal f”.

The simulation result of Example 3 is as follows.

2-2.Register

It is a memory element that memorizes the most recent input value at the rising edge of a clock signal.
Declaration method of the register is as follows.

reg Register_name = Initial_value

The initial value may be omitted.
In addition, the natural number in decimal can be input as an initial value
besides Verilog-HDL compatible and C Language compatible one.

When a value is assigned to the register in an operation description,
it is described as follows using the sign “:=” different from “data terminal” and “wire”.

Register_name := Value

The assigned value is memorized at the clock next to the one when assigned.
And, the assignment sign “=” is used when a value of the register is assigned.

Signal_name = Register_name

Let’s see Example 4 as a usage example of the register.

<<Example 4.Usage example of register>>
declare ex04 {
   input a, b ;
   output f ;
}
module ex04 {
   reg r ;

   r := a & b ; //Expression 1
   f = r ;      //Expression 2
}

Expression 1 of this Example 4 indicates an operation that
“logical AND of “a” and “b” is assigned to the register r”.
And, Expression 2 indicates an operation that
“the register r is assigned to the data output terminal f”.
The logical simulation result is shown as follows.