RAM_PROM.nsl

/* ************************************************************ */
declare RAM_PROM {

    input       AD_i[3] ;       // Address (in)
    output      DB_o1[8] ;      // Read Data (out)  / Asynchronous
    output      DB_o2[8] ;      // Read Data (out)  / Clock synchronous
    
    input       CS_i ;          // Chip select (in)
    input       REN_i ;         // Read enable (in)
}

/* ************************************************************ */
// Declare module
module RAM_PROM {

/* ************************************************************ */
// Internal operation signals
    mem mem_array [8][8] = { 0x01, 0x02, 0x03, 0x04,    // C like statement
                             8'b10010110,               // Binary data
                             8'o70,                     // Octal data
                             8'd254,                    // Decimal data
                             8'hAC                      // Hex decimal data
                           } ;
            // In this case, initial values are setted as follows :
            // mem_array[0] = 1
            // mem_array[1] = 2
            // mem_array[2] = 3
            // mem_array[3] = 4
            // mem_array[4] = 0x96
            // mem_array[5] = 0x38
            // mem_array[6] = 0xFE
            // mem_array[7] = 0xAC

    reg     clocked_rdout[8] ;

/* ************************************************************ */
// Equation
{
// Asynchronized output
    if ( CS_i & REN_i ) {
        DB_o1 = mem_array[AD_i] ;
    } else {
        DB_o1 = 8'h00 ;
    }

// Clock synchronized output
    if ( CS_i & REN_i ) {
        clocked_rdout := mem_array[AD_i] ;
    } else {
        clocked_rdout := 8'h00 ;
    }
    DB_o2 = clocked_rdout ;

}

/* ************************************************************ */
}