15word x 8bit width synchronous FIFO sample

<< Function description >>

File name
Main feature
15word x 8bit FIFO module
Signal list
DB_i[8]= Write Data in
DB_o[8] = Read Data out

WEN_i= Write Enable in
REN_i= Read Enable in

This code shown an example of FIFO module.
A number of store count is of defined number minus 1.
Thus, this code is able to store 15words.

At a ‘WEN_i’ is setted to ‘H’ level, internal FIFO store a data on ‘DB_i’ bus.
Also, at a ‘REN_i’ is setted to ‘H’ level, internal FIFO put a data on ‘DB_o’ bus.

After reset signal is released ( de-active ), FIFO will be operated, as follows :
1. Since, a ‘WEN_i’ is ‘L’ and nothing to store data, thus ‘EMPTY flag’ is ‘H’.
2. When a ‘REN_i’ is ‘L’, a ‘WEN_i’ signal is asserted to ‘H’, FIFO module store a data upto 15words.
If store position is maximum, ‘FULL flag’ will be ‘H’.
3. An operation is not gurantee at ‘READ and WRITE’ operation on sametime at FIFO-EMPTY situation.
&A “MEM” declare statement inferences memory array.

mem[sigName][n][m]= { init value … } ;
This above statement generates a “sigNAME” memory block with n[word] by m[bit] parameter.
Also, user can specify initial value using “{ }” statement.