4bit F/F sample with AR ( Databus sample )

< Function description >

File name
An one piece Flip-flop example. Asynchronous reset.

I/O signal:
D_in= Data Input (D).
ENB_in= Clock enable.
Q_out= Data Output (Q).

This code shown an example of D-Type F/F with Asynchronous reset circuit.
At the ‘ENB_in’ will be asserted to the ‘H’ level, a signal on ‘D_in’ is transfered to a ‘Q_out’ output pin.
An asynchronous reset signal is automatically used in synthesis phase.

Designer is able to set an initial value to declarated register as ‘reg [_SigName]‘ statement.
An initial value will be setted at a name of ‘p_reset’ asynchronous reset signal is asserted.

If designer wants to need a synchronous reset sample, please see ‘FF_4bit_SR.nsl’ code.

NSL language specification does not arrow to assign register equation to output pin, directoly.
This reason is depend on a SILICON layout of the F/F(register) is included in I/O pin.

Desiner should separate a statement both register equation on internal circuit and connect it to output pin.

NSL language specification does not allow a signal assign to single register which is declared multi-register declaration.
A following statement will be occured syntax-error problem.

-> Please refer a “ERROR!!!!! Flip-Flop equation”
if ( ENB_in ) {
Dtype_FF[3] : = D_in[3] ;// Capture NEW data. Bit3
Dtype_FF[2] : = D_in[2] ;// Capture NEW data. Bit2
Dtype_FF[1] : = D_in[1] ;// Capture NEW data. Bit1
Dtype_FF[0] : = D_in[0] ;// Capture NEW data. Bit0