1bit F/F sample with synchronous reset.

< Function description >

File name
An one piece Flip-flop example. Synchronous reset.
I/O signal:
D_in= Data Input (D).
SR_in= Synchronous reset input.
ENB_in= Clock enable.
Q_out= Data Output (Q).
This code shown an example of D-Type F/F with Synchronous reset circuit.
At the ‘SR_in’ signal is asserted to the ‘H’ level, a signal on ‘D_in’ will be initial value.
Also, at the ‘ENB_in’ is asserted to the ‘H’ level, a signal on ‘D_in’ will be transfered to a ‘Q_out’ output pin.
An asynchronous reset signal is automatically used in synthesis phase.
Designer is able to set an initial value to declarated register as ‘reg [_SigName]‘ statement.
An initial value will be setted at a name of ‘p_reset’ asynchronous reset signal is asserted.
However, at designer want to need a synchronous reset, it does not need implicit initial value to ‘reg’ declaration section.
If designer wants to need an asynchronous reset sample, please see ‘FF_1bit_AR.nsl’ code.
NSL language specification does not arrow to assign register equation to output pin, directoly.
This reason is depend on a SILICON layout of the F/F(register) is included in I/O pin.

Desiner should separate a statement both register equation on internal circuit and connect it to output pin.