Revision History
- Ver.20110725
- System-Task
- Add _init,_delay.
- Fix crash trouble when use some options.
- SystemC
- Add _readmemh/_readmemb system-task.
- Fix over 65bit width signal.
- Fix signed over 32bit signal is rounded signed over 32bit signalproblem.
- Fix signal type in simulation template.
- Fix 1bit inout signal is synthesised sc_logic signal problem.
- Fix any problem.
- Fix bit extended with signed problem.
- Fix _nsl_readmem function in simulation template.
- VHDL
- Fix compare 1bit signal and immediate number problem
- Fix bit combine in memory index problem
- Fix intermediate signal name in state block problem.
- Fix 1bit std_logic_vector signal problem.
- Fix bit shift problem.
- Fix when problem
- Fix signal index problem.
- Support GHDL compatible VHDL output
- Fix inout signal circuit problem.
- Fix variable signal name in VHDL code problem.
- Verilog HDL
- Fix large decimal number with sign synthesis problem.
- Ver.20110305
Fix SystemC output for SystemC verification.
Fix bit clipping problem.
Add warning message
- Ver.20110119
Fix VHDL synthesis.
Fix #undef problem.
- Ver.20110102
Fix VHDL synthesis.
Fix GUI button focus.
Expand GUI log area.
