FAQ

How long can current design methods be used?
We cannot provide precise dates. However, we are gradually integrating design methods that are being newly developed worldwide, e.g., SystemC, System Verilog, Simulink HDL.
What is the benefit of incorporating object orientation in design?
By incorporating the concept of object orientation in design, designers gain the following advantages:
1. Improved readability of source codes.
2. Improved designed data re-use.
3. Improved maintainability.
Is there any merit in using NSL Overture in the midst of a full workload?
NSL Overture expedites design completion more efficiently than other competitors and improves product quality.
We are currently using Verilog HDL and VHDL for designing, but the simulation duration seems excessively long. Do you have any suggestions?
Our solution is to synthesize the SystemC code for simulation. SystemC processes at speeds several to hundreds of times faster than earlier simulation programs and is C programming compatible.
Effective and high-speed verification can be obtained with our solution.
SystemC is becoming the mainstream language overseas and I have heard that some major corporations are using it as their design method. Does NSL Overture support SystemC ?
With NSL Overture, SystemC language can be synthesized from NSL. Generated codes are directly compatible with SystemC verification software.
What is NSL?
It is a type of hardware description language that requires less description for circuits because it allows for high levels of abstraction compared to Verilog HDL and VHDL of the past. Moreover, both hardware engineers and software engineers will find the language easy to use.
Can NSL tools be used for ASIC development?
Yes.
We use NSL Overture for LSI development of 90nm /structured ASIC for medical devices.
What is an NSL Overture?
NSL Overture is our own software packaged into an integrated development environment. The software not only includes Logic Synthesis Engine NSL Core, NSL Editor and UML Class diagram tool, it also includes a UML to NSL conversion tool and the provision of an Eclipse base framework to integrate all of the above.
Is it possible to design a multiphase clock asynchronous circuit?
Yes, it is possible. This is where NSL differs greatly from other ESL tools such as SystemC.
With NSL, if the circuit is compatible with Verilog HDL and VHDL, then it can be described in the same way.
However, we do not recommend designing multiphase clocks within the module as it destroys readability.
How can I design a multiphase clock with NSL coding?
The designer should design based on a single phase clock and connect it at net level with the main module using “interface” syntax.
We provide sample codes using “interface” syntax.
What is the level of readability of Verilog HDL and VHDL codes generated by NSL logic synthesis tools?
Logic Synthesis Engine NSL Core is not simply a language conversion tool. It conducts logic synthesis and optimization processing, generating codes that are RTL level compressed codes.
Thus, although it is readable, it is similar to assembly language derived from C language making readability unnecessary.
Can NSL be used for codes already designed with Verilog HDL and VHDL?
Yes.
The already existing IP core can be used as a submodule by declaring a port-map with “interface” syntax.
It can be used by instantiating the submodule and connecting the wiring to the main module. This method facilitates the use of PLL and BlockRAM in FPGAs and CPU Core.
For what applications is NSL most advantageous?
It is especially useful for design applications with heavy usage of pipelines that are frequently changed.
- Pipeline design
- Digital signal processing
- IP core/IP library management
- Cache memory and CAM (Content Addressable Memory)
Why was NSL used instead of other ESL such as SystemC and System Verilog?
Other ESLs were primarily for verification and did not focus on LSI development. LSI development work, as defined here, includes the finite control of asynchronous/synchronous circuits and connections with other IP libraries.
How much training is required to be able to design beginner-level standard logic circuits?
A few hours of training are sufficient.
With design experience in Verilog HDL or VHDL, technical skills can be obtained in a short period of time.
NSL is very similar to C/C++ language and Verilog HDL. Language formulation is such that operations can be easily understood by simply scanning syntax.
How much training is required to be able to design a medium-scale class SDRAM controller and 16bit processer?

It depends on one’s design proficiency, but for someone with Verilog HDL or VHDL circuit design experience, it should only require about 10~20 hours.
-Circuit design can be performed by understanding the describing methods and operations listed below:
-parallel operation description/sequential operation description.
-State machine description/arbitration/layer design.
-Main module and submodule handshake.
>-Process design is an effective training method.

-8Bit/16Bit small-scale and muticycle processor design is possible within about 10 hours. Pipeline versions are possible within about 15 hours.

I already have Verilog HDL/VHDL LSI development and functional verification environments. Are these environments compatible with NSL design environments?
Yes, existing environments can be used.
The NSL Core synthetic engine will generate source codes for System C language and standard RTL design languages such as Verilog HDL or VHDL.
That is why it is possible to continue to use LSI development and functional verification environments.
How long will it take to master verification methods using existing Verilog HDL/VHDL?
No certain amount of time is required.
NSL Core synthetic engines generate RTL level Verilog HDL/VHDL codes, so it is possible to continue the use of earlier verification methods.
Are any verification functions available with NSL Overture?

1)NSL specification level :
Can be embedded in NSL codes used for verification in Verilog HDL.

2) NSL simulator:
We recommend the following verification methods:
-Verilog HDL: Has adequate functionality in popular technologies. ASIC vendors accept it as a sign-off simulation, as well.
-SystemC: A new high-speed technology.

(VHDL: Stream processing is weak and is thus not recommended)

Is NSL Overture merely a language conversion tool?
No, it is not simply language conversion tool.
Dr. Naohiko Shimizu, who also worked on the development of NSL formulation and NSL Core at IP-ARCH, Inc., conducted supercomputer logic circuit design. NSL incorporates Dr. Shimizu’s technologies.
Typically, the problem with other ESL tools and C/C++ language based development tools is that, after language conversion, the scale of design becomes too bloated resulting in sluggish processing. With NSL Core, however, after optimal processing and synthetic processing of described units, NSL converts them into each type of generated language. As a result, a more efficient circuit can be obtained compared to other ESL. Further, it has the advantage of design code readability and maintainability. NSL incorporates object oriented technology.
Do NSL specification and logic synthetic tools support both function description and function validation?

Yes.

・operation description/function description
-System level description
-Behavior description
-RTL (gate-level) description

・Function validation description
-Verilog HDL language-like validation syntax

Can libraries such as PLI (Verilog HDL) and FLI(VHDL) be used with NSL?
No. Such functions are not available. If you want to use them, create a test vector with corresponding language tools.
Do you offer NSL Overture in integrated development environments?
Yes, we provide integrated development environments. Our products are integrated with Eclipse 3.5 Galileo.
I already have Verilog HDL/VHDL LSI development and functional verification environments. Are these environments compatible with the NSL Overture development environment?
Yes, you can continue to use older environments. The installation of NSL Overture should not be considered the replacement of previous environments, but rather a tool for streamlining previous environments.
Continued use of LSI development/functional verification environments is possible because NSL Overture generates standard RTL design languages such as Verilog HDL and VHDL and SystemC source codes from NSL.
I already have Verilog HDL/VHDL LSI development and functional verification environments. Are these environments compatible with the NSL Overture development environment?
Yes, you can continue to use older environments. The installation of NSL Overture should not be considered the replacement of previous environments, but rather a tool for streamlining previous environments.
Continued use of LSI development/functional verification environments is possible because NSL Overture generates standard RTL design languages such as Verilog HDL and VHDL and SystemC source codes from NSL.
What kinds of UML/NSL sample codes are available?

More than 40 types of codes have been released.
More new codes are expected, as well.

-Standard logic circuit (And / Or / Inv/ etc.), state machine sequential circuits
-Asynchronous serial, SDRAM controller, PCI
-8bit MCU, 16bit MPU, 32bit MIPS/V1

How are products updated?
They can be manually updated from an update menue in NSL Overture.
Our company already has numerous IP cores. As we will have to develop a new IP core library using NSL, will an efficient management system be available?
e provision of library management tools is currently under consideration.
We have plans to provide tools for integrated “object” management of NSL / UML / Verilog HDL / VHDL / SystemC and text files that is different from Xilinx, Inc.’s EDK and Altera Corporation’s SOPC Builder.