Products

Embedded systems in recent year are becoming large-scale with multifunction. Amid improvement of design productivity is required in semiconductor device development, we propose the model base design method, “UML (Unified Modeling Language) to RTL” with own hardware description language (NSL: Next Synthesis Language) and its synthesis engine.

This new technique is to connect UML diagram used in the upstream process of product development with RTL written by the existing hardware description language seamlessly through behavioral description with the high degree of abstraction level used in NSL.

With this new technique“UML to RTL”, it improves the productivity of engineers and also to realize the competitive advantage to enhance the critical architecture design capabilities in upstream process of product development. Eventually you are able to gain significant competitive advantage. In addition, it can smooth out the transmission of information between the parties by sharing design information of specifications and features in the development group.

NSL-Overture

Value of “UML to RTL” method

Reduction of a man-hour of development(Front-end Design efficiency is 50% UP)
  • NSL source code which is described compendiously due to structure and syntax of NSL, has good readability. (1/4 times smaller than Verilog-HDL code)
  • Able to information sharing and smooth communication in the development group member by means of UML diagrams. (Reduction of the wasted time for the meeting and the making of document)
Eliminating the distinction between the engineers (skill gap)
  • Homogenizing of outputted RTL code file. In fact, a beginners’ class engineer can realize the optimal circuit (speed performance and scale) which is the same as an expert level.
A low-cost environment development (max 50% cost cut)
  • It is not necessary to design and to manage individually of RTL model (Verilog HDL/VHDL/SytemC). Able to consolidate design property such as IP core by means of NSL model.
  • Able to create handily the hardware software Co-verification environment by outputted SystemC model.

In case of Design House,
Reduction in their man-hour cost of design that is enhance their business competitiveness.

In case of IP Provider,
Reduction in development / maintenance cost for IP Core. (50% cost cut)

In case of Manufacturer/Service Provider,
Enhance the design efficiency of upper process, such as architecture and algorithm design, so enhance their business competitiveness.
(Reduction in their waste meetings and documents)

Product Family

◇Product name NSL Overture:
“NSL Overture” is Integrated Development Environment of embodied new method “UML to RTL”. This core technology is new-generation hardware description language NSL and a behavior synthesis engine (NSL Core) provided by Overtone Corporation.
◇Product name NSL Core:
“NSL Core” is a behavior synthesis engine for our NSL code file, which generate RTL format file (Verilog HDL, VHDL, SystemC).
◇Product IP Core models:
The model (IP core) which was developed by UML/NSL.

<System Requirements (Recommended system environment)>

Item NSL Core NSL Overture
Processor (Clock) 1GHz or faster 2GHz or faster
Memory 256MB or more 1GB or more
Display 1024×768 or higher resolution
Hard Disk (HDD) 25MB available disk space 512MB available disk space
Operating System Windows 7/10 (Linux is work in progress)
Java Runtime Java5(JRE5/JDK5) or later/td>
Internet Connection For the updating